This applications claims the priority benefit of Taiwan application serial no. 87117426, filed Oct. 21, 1998, the full disclosure of which is incorporated herein by reference.
1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating an embedded dynamic random access memory device.
2. Description of Related Art
An embedded dynamic random access memory (DRAM) device is a kind of device that includes a memory array and a logic circuit array formed together in a single integrated circuit (IC) chip. This embedded DRAM therefore can access a large amount of data with much higher accessing speed so that the embedded DRAM with its advantages is widely used in a logic circuit, which is used for a purpose to process a large amount of data, such as a graphic or an image microprocessor. An accomplished embedded DRAM, typically includes a logic circuit, a transfer field effect transistor (transfer FET) array, and a capacitor coupled to the transfer FET, in which the transfer FET serves as a lower electrode of the capacitor and a selective switch when the transfer FET is selected by a bit line. The voltage status of the capacitor can therefore be read or changed through the transfer FET. One FET typically includes a gate structure and an interchangeable source/drain region at each side of the gate structure. The capacitor is coupled to the interchangeable source/drain region at one side of the gate structure, which typically is the source region.
FIGS. 1A-1E are cross-sectional views of a portion of a semiconductor substrate, schematically illustrating a conventional fabrication process for forming an embedded DRAM. In FIG. 1A, an isolation structure 102 is formed on a semiconductor substrate 100 so as to form a DRAM active area 170 and a logic active area 180 on the substrate 100. A DRAM transfer FET is to be formed on the DRAM active region 170, and a logic transfer FET included in a logic circuit is to be formed on the logic active region 180. In order to obtain a smaller gate resistance, a formation of a gate includes depositing a polysilicon layer on the substrate 100, forming a silicide layer on the polysilicon layer to form a polycide layer, and patterning the polycide layer. An alternative method is first depositing a patterned polysilicon layer on the substrate 100, performing a self-aligned silicide (Salicide) process to form a Salicide layer on all exposed silicon surface of the patterned polysilicon and an interchangeable source/drain region. However, the Salicide process usually consumes the junction depth to cause a shallow junction, which may further cause a charge leakage of the capacitor. The DRAM device may results in a failure at the end. A strategy combining above two methods is then proposed. In the embedded DRAM, a gate structure is usually formed by a polysilicon layer and a silicide layer through deposition. The interchangeable source/drain region of a transistor belonging to the DRAM is not formed with a Salicide layer so as to avoid the charge leakage. But, the interchangeable source/drain region of a transistor belonging to the logic circuit is formed with a Salicide layer to reduce its sheet resistance so that the logic circuit has faster operation speed. In order to form the Salicide layer only on the logic transistor, a conventional method is described in the following.
In FIG. 1A, a usually thin oxide layer 104 is formed over the substrate 100. A polysilicon layer 106 and a silicide layer 108 are sequentially formed on the oxide layer 104. This two layers 106, 108 are usually called together as a polycide layer. A cap layer 110 is formed on the silicide layer 108.
In FIG. 1B, patterning the cap layer 110, the silicide layer 108, the polysilicon layer 106, and the oxide layer 104 forms a gate structure 112 on the DRAM active area 170 of FIG. 1A, and a gate structure 114 on the logic active area 180 of FIG. 1A. The gate structure 112 includes a cap layer 110a, a silicide layer 108a, a polysilicon layer 106a, and the oxide layer 104a; and the gate structure 114 includes a cap layer 110b, a silicide layer 108b, a polysilicon layer 106b, and the oxide layer 104b. Using the cap layers 110a, 110b as a mask, an interchangeable source/drain region 128 and an interchangeable source/drain region 130 are respectively forms in the substrate 100 at each side of the gate structure 128 and the gate structure 130.
In FIG. 1C, an annealing process at a temperature of 900xc2x0 C.-1000xc2x0 C. is performed to uniformly diffuse the implanted ions so that the interchangeable source/drain regions 128, 130 become the interchangeable source/drain regions 128a, 130a. So, each of the DRAM active area 170 an the logic active area 180 of FIG. 1A respectively have a formed DRAM FET and a formed logic FET. The DRAM FET includes the gate structure 112 and the interchangeable source/drain regions 128a, and the logic FET includes the gate structure 114 and the interchangeable source/drain region 130a. A spacer 120 is formed on each sidewall of the gate structure 112 and a spacer 122 is formed on each sidewall of the gate structure 114. In order to decrease the sheet resistance of the interchangeable source/drain region 130a of the logic FET at the logic active area 180 of FIG. 1A, a Salicide layer is desired to be formed on the interchangeable source/drain region 130a, but not on the interchangeable source/drain region 128a of the DRAM FET. A typical process is forming an insulating layer 132 over the DRAM FET. A Salicide process is performed by first forming a metal layer 134 over the substrate 100.
In FIG. 1D, a rapid thermal process (RTP) is performed to trigger a reaction between silicon of the interchangeable source/drain region 130a and the metal layer 134 so as to form a Salicide layer 136 on it. Using a mix acid solution of H2O2 and NH4OH as an etchant, a wet etching process is performed to remove the metal layer 134 without reaction.
In FIG. 1E, a dielectric layer 140 is formed over the substrate 100. The dielectric layer 140 is patterned to form a contact opening 142 to expose the interchangeable source/drain region 128a of the DRAM FET at one side of the gate structure 128a. A capacitor 150 including a polysilicon layer 144 serving as a lower electrode, a dielectric film layer 146, and a polysilicon upper electrode 148 is formed on the dielectric layer 140. The capacitor 150 is coupled to the DRAM FET through the contact opening 142. The DRAM FET with the capacitor 150 is accomplished.
In the conventional fabrication method describe above, the thickness of the gate oxide layer 104a of the gate structure 112, shown in FIG. 1B, for the DRAM FET is equal to the thickness of the gate oxide layer 104b of the gate structure 114 for the logic FET. In an actual operating condition, the DRAM FET is applied with a higher bias than a bias applied on the logic FET. This causes the gate oxide layer 104a of the DRAM FET needs to endure a higher bias than the gate oxide layer 104b of the logic FET. If the gate oxide layers 104a, 104b are formed with a greater thickness suitable for the DRAM FET, the logic FET may not be activated. If the gate oxide layers 104a, 104b are formed with a smaller thickness suitable for the logic FET, the DRAM FET may get a breakdown.
On the other hand, in order to reduce the gate resistance of the gate structure 112 of the DRAM FET and avoid a charge leakage due to shallow junction occurring on the interchangeable source/drain region 128a, both gate structures 112 and 114 respectively having the polysilicon layer 106a and 106b, and the silicide layers 108a and 108b. In this strategy, even though the gate resistance of the DRAM FET is reduced, the operating performance of the logic FET is reduced.
It is therefore an objective of the present invention to provide a method for fabricating an embedded DRAM so as to have a suitable different gate oxide thickness for a DRAM FET and a logic FET. When the DRAM FET and the logic FET are applied with a different bias, they can properly work without the phenomena that the DRAM FET gets a breakdown or the logic FET cannot be activated.
It is another an objective of the present invention to provide a method for fabricating an embedded DRAM so as to reduce a gate resistance of a DRAM FET and increase the performance of a logic FET.
It is still another an objective of the present invention to provide a method for fabricating an embedded DRAM so as to reduce a sheet resistance of a junction region of a logic FET so that the logic performance is improved. A junction depth of a DRAM FET is also maintained so as to prevent a charge leakage of a coupled capacitor from occurring.
In accordance with the foregoing and other objectives of the present invention, a method for fabricating an embedded DRAM is provided. The method includes doping a semiconductor substrate, which has a DRAM region and a logic region, at desired active areas with different dopant concentration for a DRAM FET and a logic FET. A thermal oxidation process is performed to form a DRAM oxide layer on the substrate at the DRAM region and a logic oxide layer on the substrate at the logic region. The DRAM oxide layer is thicker than the logic oxide layer. A polysilicon layer is formed over the substrate. A silicide layer and a cap layer are formed on the polysilicon layer at the DRAM region. A DRAM gate is formed by patterning all layers on the substrate at the DRAM region, and a logic semi-gate is formed by simultaneously patterning all layers on the substrate at the logic region. The logic semi-gate is partially done at the current stage.
Using the DRAM gate and the logic semi-gate as a mask, a DRAM lightly doped region and a logic lightly doped region in the substrate respectively at each side of the DRAM gate and the logic semi-gate are formed. A DRAM spacer and a logic spacer are respectively formed on each sidewall of the DRAM gate and the logic semi-gate. Using the DRAM gate, the logic semi-gate, and all the spacers as a mask, a DRAM heavily doped region and a logic heavily doped region in the substrate respectively at each side of the DRAM gate and the logic semi-gate are formed. Each lightly doped region and each heavily doped region form two interchangeable source/drain regions with a lightly doped drain (LDD) structure. The one in the DRAM region is called a DRAM interchangeable source/drain region, and the one in the logic region is called a logic interchangeable source/drain region. An annealing process is performed to obtain a better dopant distribution in the interchangeable source/drain regions at the DRAM region and the logic region. Due to the annealing process, a native oxide layer is simultaneously formed over the substrate. A portion of the native oxide layer on the logic region is removed so as to expose the logic semi-gate and the substrate. A Salicide process is performed to form a Salicide layer on the logic interchangeable source/drain region and the logic semi-gate, which with the Salicide layer becomes a logic gate.
A capacitor is formed on the DRAM interchange source/drain by forming a dielectric layer over the substrate, patterning the dielectric layer to form a contact opening in the dielectric layer to expose the DRAM interchangeable source/drain region at one side of the DRAM gate. A lower electrode is formed to have a coupling with the DRAM interchangeable source/drain region through the contact opening. A conformal dielectric film layer is formed over an exposed upper portion of the lower electrode on the dielectric layer. An upper electrode is formed over the dielectric film layer so that the capacitor is formed with a coupling to the DRAM interchangeable source/drain region.